1. Field of the Invention
The present invention relates to a silicon wafer and production technology therefor which is capable of suppressing generation of both slip dislocations and warpage, in a field of production technology of semiconductor wafers, in particular, device production processes.
2. Background Art
Silicon wafers to be used as a substrate for producing semiconductor devices are produced by slicing a single crystal silicon ingot, and performing heat treatment or mirror finishing or the like. Due to the ease of obtaining single crystal ingots having a large diameter, or in controlling defects, most single crystal silicon ingots are produced by a Czochralski (“CZ”) method. A silicon single crystal silicon grown by such a CZ method (“CZ-Si”) has internal “Grown-in defects,” in particular, supersaturated oxygen taken into the silicon lattice in a supersaturated state, which causes formation of micro defects known as Bulk Micro Defects (“BMD”), during a subsequent heat treatment (anneal).
In general, BMDs existing inside a crystal just after single crystal silicon growth (Grown-in defect, an oxygen deposit, dislocation, lamination defect or the like induced in a device production process) deteriorates device characteristics, and therefore it is required that there are no crystal defects in a formation region of a semiconductor device. However, on the other hand, it has also been revealed that BMDs can be utilized effectively as a gettering site for heavy metals or to increase the mechanical strength of the substrate, and thus at present, generation of a suitable amount of BMDs inside a silicon wafer is required.
In order to satisfy such requirements, there is generally used at present a method for forming an Intrinsic Gettering layer (hereafter referred to as “an” IG layer”) by annealing the silicon wafer at high temperature and inducing BMD formation inside the silicon wafer, as well as forming a Denuded Zone layer (hereafter referred to as a “DZ layer”) having extremely low crystal defects by eliminating grown-in defects near the surface of the silicon wafer.
However, the DZ layer formed on the front and rear surfaces of the silicon wafer by the annealing process at high temperature decreases the number of BMDs or dislocations, which together with oxygen or oxygen impurities or the like, results in an extreme decrease of oxygen concentration by outward diffusion of oxygen during heat treatment, and in turn extremely decreases suppression of the extension of dislocation defects at the front and rear surfaces of the silicon wafer. Therefore, dislocation defects (hereafter referred to as “slip”) easily extend into the bulk from minute flaws on the front and rear surfaces, introduced in the annealing step, creating the problem that the strength of the silicon wafer decreases due to extension of such slip dislocations. Furthermore, such decrease of silicon wafer strength can result in wafer damage or wafer destruction during production steps. However, the DZ layer is indispensible in semiconductor device formation, therefore, silicon wafers which have a DZ layer and yet exhibit excellent strength properties are desired. In particular, when annealing is performed on a wafer supported by a heat treatment susceptor or the like, a slip dislocation often extends from the part supported by the susceptor, because of a dislocation generated at the contact point of the silicon wafer and the susceptor. In addition, a slip dislocation may extend from the edge part of the silicon wafer.
In addition, in order to produce a device such as once having a thermally oxidized film, or activation of a dopant injected into a source or drain region, heat treatment of the silicon wafer is essential. In general, heat treatment is classified as: batch heat treatment, where one treatment is performed by assembling longitudinally several tens to hundreds or more of wafers held horizontally; and single wafer heat treatment, where heat treatment is performed wafer by wafer. In heat treatment, generation of a temperature gradient on the silicon wafer surface causes thermal stress on the surface in proportion to the gradient, and a thermal stress of over a certain value raises a problem of not only minute level differences on the wafer surface, or the slip previously mentioned, but also causes warpage of the silicon wafer.
Technologies to suppress and prevent the generation of such slip dislocation or warpage are known. For example, in JP-A-2008-166721, there is disclosed a technology to produce a silicon wafer, in which a predetermined amount of plate-like BMDs are formed and an inter-lattice oxygen concentration is less than or equal to 5×1017 atoms/cm3, by performing heat treatment at a temperature range of 600 to 750° C. for 10 minutes to 10 hours, and then increasing the temperature up to 1000° C. at a rate of 0.1° C./minute to 1° C./minute for 5 to 50 hours, and further subjecting the silicon wafer to heat treatment at a temperature range of 1000 to 1250° C. so that the diffusion length of inter-lattice oxygen is below 20 to 30 μm.
In addition, in JP-A-2008-160069, there is disclosed a technology to produce a silicon wafer, in which a predetermined amount of octahedral BMDs are formed and an inter-lattice oxygen concentration is less than or equal to 5×1017 atoms/cm3, by performing heat treatment at a temperature range of 600 to 750° C. for 30 minutes to 10 hours, and then the increasing the temperature up to 1000° C. at a rate of 0.1 to 1° C./minute for 5 hours to 50 hours, and by further subjecting the silicon wafer to heat treatment at a temperature range of 1000 to 1250° C. so that the diffusion length of inter-lattice oxygen is 30 μm to 50 μm.
Further, in JP-A-2009-164155, there has been disclosed a technology to control the change of substitution-type carbon concentration and inter-lattice oxygen concentration inside a silicon wafer to be within a predetermined range before and after heat treatment in a heat treatment furnace by a low temperature heat treatment of 650 to 800° C., thereafter setting a maximal temperature at 700 to 1000° C. and increasing the temperature at a rate of 0.1 to 2° C./minute; removing the silicon wafer at 600° C. to 800° C.; further inserting the silicon substrate inside a heat treatment furnace at a furnace temperature of 600 to 800° C.; increasing the temperature of the heat treatment furnace at a rate of 5 to 10° C./minute in a temperature range from the insertion temperature up to below 1100° C.; increasing the temperature of the heat treatment furnace at a rate of 1 to 2° C./minute in a temperature range of 1100 to 1250° C.; and keeping the temperature of the heat treatment furnace constant within the range of 1000° C. to 1250° C.; thus performing a heat treatment at a high temperature of 1100 to 1250° C.
FIG. 1 shows a schematic diagram of a typical example of slip and warpage introduced by heat treatment. The slip is introduced from a contact point of the rear surface of the wafer and a wafer holding member or from the edge of the wafer. The introduced slip extends in a 110 direction and incurs wafer damage or destruction depending on the case. The warpage is a phenomenon that the wafer deforms due to thermal strain in heat treatment. For example, a wafer of the 100 plane, as shown in FIG. 1, may exhibit concave-type warpage. Usually, warpage of the silicon wafer, before heat treatment is performed to bring desired characteristics, is less than or equal to 10 μm. However, the heat applied by heat treatment may generate a concave-convex height difference of the silicon wafer that reaches several tens of μm. Increased warpage disturbs correct exposure of a semiconductor device pattern on the wafer surface, and causes decreased yield of the semiconductor device.
The warpage problem tends to be significant when the wafer diameter is greater than or equal to 200 mm, and is also significant when the heat treatment step of the device is performed at high temperature over a long time. On the other hand slip dislocation decreases when the BMD concentration increases, and warpage increases when the BMD concentration increases. Thus, it is known that slip and warpage are in a trade-off relationship. Accordingly, there still is a problem that generation of slip and warpage, in particular, generation of warpage, cannot be suppressed and prevented effectively. The total density of BMDs inside the silicon wafer can only be increased to a high concentration by the technology as disclosed in JP-A-2008-166721 and JP-A-2008-160069, in which the concentration of relatively large BMDs is decreased to suppress and prevent generation of warpage, the density of relatively small BMDs is increased to suppress and prevent generation of slip or slip length, and further, BMD shape is controlled to a predetermined morphology such as plate or octahedron to suppress and prevent generation of slip or slip length, so as to adjust inter-lattice oxygen concentration and then to secure oxygen adhered to BMD to the predetermined amount.
In addition, there is a problem that warpage cannot be suppressed and prevented effectively by the method as disclosed in JP-A-2009-164155, by the number of oxygen or carbon atoms adhered to BMDs by performing heat treatment so as to maintain carbon concentration and oxygen concentration in the silicon wafer as much as possible before and after heat treatment to the predetermined amount, although generation of slip or slip length can be suppressed to some extent.